A FPGA pipelined backward adaptive scalar quantizer

Oswaldo Cadenas; Graham Megson

A FPGA pipelined backward adaptive scalar quantizer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A fully pipelined implementation in FPGA hardware of a backward adaptive scalar quantizer known as Jayant quantizer is presented. The implementation combines a fast systolic formulation of a uniform scalar quantizer with a multi-phase pipeline clocking mechanism based on embedded Delay-Locked Loops (DLLs) of modern FPGA devices. This combination shows that traditional fixed quantization based on look-up tables can be replaced by dynamic and adaptive quantizer circuits fast and small enough to be integrated into totally hardware solutions of standard lossy compression techniques.

Original language	English
Title of host publication	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems
Editors	M.H. Rashid
Pages	410-415
Number of pages	6
Publication status	Published - 2004
Externally published	Yes
Event	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems - Clearwater Beach, FL, United States Duration: 28 Nov 2004 → 1 Dec 2004

Publication series

Name	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

Conference

Conference	Proceedings of the IASTED International Conference on Circuits, Signals, and Systems
Country/Territory	United States
City	Clearwater Beach, FL
Period	28/11/04 → 1/12/04

Keywords

Adaptive quantization
DLLs
FPGA
Jayant Quantizer
Multi-phase clocking
Pipeline

Cite this

@inproceedings{cd8a24cd03d24fa4846cfe150e4a385c,

title = "A FPGA pipelined backward adaptive scalar quantizer",

abstract = "A fully pipelined implementation in FPGA hardware of a backward adaptive scalar quantizer known as Jayant quantizer is presented. The implementation combines a fast systolic formulation of a uniform scalar quantizer with a multi-phase pipeline clocking mechanism based on embedded Delay-Locked Loops (DLLs) of modern FPGA devices. This combination shows that traditional fixed quantization based on look-up tables can be replaced by dynamic and adaptive quantizer circuits fast and small enough to be integrated into totally hardware solutions of standard lossy compression techniques.",

keywords = "Adaptive quantization, DLLs, FPGA, Jayant Quantizer, Multi-phase clocking, Pipeline",

author = "Oswaldo Cadenas and Graham Megson",

year = "2004",

language = "English",

isbn = "0889864551",

series = "Proceedings of the IASTED International Conference on Circuits, Signals, and Systems",

pages = "410--415",

editor = "M.H. Rashid",

booktitle = "Proceedings of the IASTED International Conference on Circuits, Signals, and Systems",

note = "Proceedings of the IASTED International Conference on Circuits, Signals, and Systems ; Conference date: 28-11-2004 Through 01-12-2004",

}

Cadenas, O & Megson, G 2004, A FPGA pipelined backward adaptive scalar quantizer. in MH Rashid (ed.), Proceedings of the IASTED International Conference on Circuits, Signals, and Systems., 449-152, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems, pp. 410-415, Proceedings of the IASTED International Conference on Circuits, Signals, and Systems, Clearwater Beach, FL, United States, 28/11/04.

A FPGA pipelined backward adaptive scalar quantizer. / Cadenas, Oswaldo; Megson, Graham.
Proceedings of the IASTED International Conference on Circuits, Signals, and Systems. ed. / M.H. Rashid. 2004. p. 410-415 449-152 (Proceedings of the IASTED International Conference on Circuits, Signals, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A FPGA pipelined backward adaptive scalar quantizer

AU - Cadenas, Oswaldo

AU - Megson, Graham

PY - 2004

Y1 - 2004

N2 - A fully pipelined implementation in FPGA hardware of a backward adaptive scalar quantizer known as Jayant quantizer is presented. The implementation combines a fast systolic formulation of a uniform scalar quantizer with a multi-phase pipeline clocking mechanism based on embedded Delay-Locked Loops (DLLs) of modern FPGA devices. This combination shows that traditional fixed quantization based on look-up tables can be replaced by dynamic and adaptive quantizer circuits fast and small enough to be integrated into totally hardware solutions of standard lossy compression techniques.

AB - A fully pipelined implementation in FPGA hardware of a backward adaptive scalar quantizer known as Jayant quantizer is presented. The implementation combines a fast systolic formulation of a uniform scalar quantizer with a multi-phase pipeline clocking mechanism based on embedded Delay-Locked Loops (DLLs) of modern FPGA devices. This combination shows that traditional fixed quantization based on look-up tables can be replaced by dynamic and adaptive quantizer circuits fast and small enough to be integrated into totally hardware solutions of standard lossy compression techniques.

KW - Adaptive quantization

KW - DLLs

KW - FPGA

KW - Jayant Quantizer

KW - Multi-phase clocking

KW - Pipeline

UR - http://www.scopus.com/inward/record.url?scp=11144333105&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:11144333105

SN - 0889864551

SN - 9780889864559

T3 - Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

SP - 410

EP - 415

BT - Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

A2 - Rashid, M.H.

T2 - Proceedings of the IASTED International Conference on Circuits, Signals, and Systems

Y2 - 28 November 2004 through 1 December 2004

ER -

A FPGA pipelined backward adaptive scalar quantizer

Abstract

Publication series

Conference

Keywords

Other files and links

Cite this