A n-bit reconfigurable scalar quantiser

Oswaldo Cadenas, Graham Megson

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Citations (Scopus)

Abstract

A reconfigurable scalar quantiser capable of accepting n-bit input data is presented. The data length n can be varied in the range 1... N - 1 under partial-run time reconfiguration, p-RTR. Issues as improvement in throughput using this reconfigurable quantiser of p-RTR against RTR for data of variable length are considered. The quantiser design referred to as the priority quantiser PQ is then compared against a direct design of the quantiser DIQ. It is then evaluated that for practical quantiser sizes, PQ shows better area usage when both are targeted onto the same FPGA. Other benefits are also identified.

Original languageEnglish
Title of host publicationField-Programmable Logic and Applications - 11th International Conference, FPL 2001, Proceedings
EditorsGordon Brebner, Roger Woods
PublisherSpringer Verlag
Pages420-429
Number of pages10
ISBN (Print)3540424997, 9783540424994
DOIs
Publication statusPublished - 2001
Externally publishedYes
Event11th International Conference on Field-Programmable Logic and Applications, FPL 2001 - Belfast, United Kingdom
Duration: 27 Aug 200129 Aug 2001

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2147
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference11th International Conference on Field-Programmable Logic and Applications, FPL 2001
Country/TerritoryUnited Kingdom
CityBelfast
Period27/08/0129/08/01

Bibliographical note

Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 2001.

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