A new organization for a perceptron-based branch predictor and its FPGA implementation

Oswaldo Cadenas; Graham Megson; Daniel Jones

doi:10.1109/ISVLSI.2005.11

A new organization for a perceptron-based branch predictor and its FPGA implementation

Oswaldo Cadenas, Graham Megson, Daniel Jones

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
Editors	A. Smailagic, N. Ranganathan
Pages	305-306
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2005.11
Publication status	Published - 2005
Externally published	Yes
Event	IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design - Tampa, FL, United States Duration: 11 May 2005 → 12 May 2005

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

Conference

Conference	IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
Country/Territory	United States
City	Tampa, FL
Period	11/05/05 → 12/05/05

Access to Document

10.1109/ISVLSI.2005.11

Cite this

Cadenas, O., Megson, G., & Jones, D. (2005). A new organization for a perceptron-based branch predictor and its FPGA implementation. In A. Smailagic, & N. Ranganathan (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design (pp. 305-306). (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI). https://doi.org/10.1109/ISVLSI.2005.11

Cadenas, Oswaldo ; Megson, Graham ; Jones, Daniel. / A new organization for a perceptron-based branch predictor and its FPGA implementation. Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. editor / A. Smailagic ; N. Ranganathan. 2005. pp. 305-306 (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI).

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abstract = "An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.",

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note = "IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design ; Conference date: 11-05-2005 Through 12-05-2005",

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Cadenas, O, Megson, G & Jones, D 2005, A new organization for a perceptron-based branch predictor and its FPGA implementation. in A Smailagic & N Ranganathan (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI, pp. 305-306, IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States, 11/05/05. https://doi.org/10.1109/ISVLSI.2005.11

A new organization for a perceptron-based branch predictor and its FPGA implementation. / Cadenas, Oswaldo; Megson, Graham; Jones, Daniel.
Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. ed. / A. Smailagic; N. Ranganathan. 2005. p. 305-306 (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Cadenas O, Megson G, Jones D. A new organization for a perceptron-based branch predictor and its FPGA implementation. In Smailagic A, Ranganathan N, editors, Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. 2005. p. 305-306. (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI). doi: 10.1109/ISVLSI.2005.11

A new organization for a perceptron-based branch predictor and its FPGA implementation

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