FPGA circuits for a Monte-Carlo based matrix inversion architecture

O. Cadenas, G. Megson, T. Plaks

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A Monte-Carlo based matrix inversion algorithm is optimized to develop an architecture that inverts a matrix of size 64 × 64. The architecture fits in FPGA Virtex-II devices and runs at a frequency over 200 MHz. It is observed that architecture practical prototypes for matrices of large sizes is not severely constrained by FPGA computational resources but by FPGA pin-out count. The study suggests to include the Markov generator in hardware to reduce the pin-out count overhead, reducing the complexity when partitioning large problems for hardware-software co-designs in favor of higher performance.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 03
EditorsT.P. Plaks, T.P. Plaks
Pages201-207
Number of pages7
Publication statusPublished - 2003
Externally publishedYes
EventProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'03 - Las Vegas, NV, United States
Duration: 23 Jun 200326 Jun 2003

Publication series

NameProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms

Conference

ConferenceProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'03
Country/TerritoryUnited States
CityLas Vegas, NV
Period23/06/0326/06/03

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