TY - GEN
T1 - Generic construction of monitors for floating point unit designs
AU - Goñi, Oscar
AU - Todorovich, Elías
AU - Cadenas, Oswaldo
PY - 2012
Y1 - 2012
N2 - This paper proposes a set of well defined steps to design functional verification monitors intended to verify Floating Point Units (FPU) described in HDL. The first step consists on defining the input and output domain coverage. Next, the corner cases are defined. Finally, an already verified reference model is used in order to test the correctness of the Device Under Verification (DUV). As a case study a monitor for an IEEE754-2008 compliant design is implemented. This monitor is built to be easily instantiated into verification frameworks such as OVM. Two different designs were verified reaching complete input coverage and successful compliant results.
AB - This paper proposes a set of well defined steps to design functional verification monitors intended to verify Floating Point Units (FPU) described in HDL. The first step consists on defining the input and output domain coverage. Next, the corner cases are defined. Finally, an already verified reference model is used in order to test the correctness of the Device Under Verification (DUV). As a case study a monitor for an IEEE754-2008 compliant design is implemented. This monitor is built to be easily instantiated into verification frameworks such as OVM. Two different designs were verified reaching complete input coverage and successful compliant results.
UR - http://www.scopus.com/inward/record.url?scp=84863908329&partnerID=8YFLogxK
U2 - 10.1109/SPL.2012.6211776
DO - 10.1109/SPL.2012.6211776
M3 - Conference contribution
AN - SCOPUS:84863908329
SN - 9781467301862
T3 - SPL 2012 - 8th Southern Programmable Logic Conference
BT - SPL 2012 - 8th Southern Programmable Logic Conference
T2 - 8th Southern Programmable Logic Conference, SPL 2012
Y2 - 20 March 2012 through 23 March 2012
ER -