@inproceedings{09f0ce6fd86242cdabc0829a284a4285,
title = "Implementation of a block based neural branch predictor",
abstract = "This paper contributes to a dynamic branch predictor algorithm based on a perceptron in two directions: Firstly, a new block form of computation is introduced that reduces theoretically by half the combinational critical path for computing a prediction. Secondly, implementation in FPGA hardware is fully developed for quantitative comparison purposes. FPGA circuits for a one-cycle block predictor produces 1.7 faster clock rates than a direct implementation of the original perceptron predictor. This faster clock allows to realize predictions with longer history lengths for the same hardware budget.",
author = "O. Cadenas and G. Megson and D. Jones",
year = "2005",
doi = "10.1109/DSD.2005.49",
language = "English",
isbn = "0769524338",
series = "Proceedings - DSD'2005: 8th Euromicro Conference on Digital System Design - Architectures, Methods and Tools",
pages = "235--238",
booktitle = "Proceedings - Thirteenth International Symposium on Temporal Representation and Reasoning, TIME 2006",
note = "DSD'2005: 8th Euromicro Conference on Digital System Design ; Conference date: 30-08-2005 Through 03-09-2005",
}