Improving mW/MHz ratio in FPGAs pipelined designs

O. Cadenas; G. Megson

doi:10.1109/DSD.2002.1115379

Improving mW/MHz ratio in FPGAs pipelined designs

O. Cadenas, G. Megson

University of Reading

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.

Original language	English
Title of host publication	Proceedings - Euromicro Symposium on Digital System Design
Subtitle of host publication	Architectures, Methods and Tools, DSD 2002
Editors	Martyn Edwards
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	276-282
Number of pages	7
ISBN (Electronic)	0769517900, 9780769517902
DOIs	https://doi.org/10.1109/DSD.2002.1115379
Publication status	Published - 2002
Externally published	Yes
Event	Euromicro Symposium on Digital System Design, DSD 2002 - Dortmund, Germany Duration: 4 Sept 2002 → 6 Sept 2002

Publication series

Name	Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002

Conference

Conference	Euromicro Symposium on Digital System Design, DSD 2002
Country/Territory	Germany
City	Dortmund
Period	4/09/02 → 6/09/02

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

Keywords

Circuit synthesis
Clocks
Computer science
Cybernetics
Design engineering
Energy consumption
Field programmable gate arrays
Logic design
Pipelines
Proposals

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/DSD.2002.1115379

Cite this

Cadenas, O., & Megson, G. (2002). Improving mW/MHz ratio in FPGAs pipelined designs. In M. Edwards (Ed.), Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002 (pp. 276-282). Article 1115379 (Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DSD.2002.1115379

Cadenas, O. ; Megson, G. / Improving mW/MHz ratio in FPGAs pipelined designs. Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002. editor / Martyn Edwards. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 276-282 (Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002).

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abstract = "This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.",

keywords = "Circuit synthesis, Clocks, Computer science, Cybernetics, Design engineering, Energy consumption, Field programmable gate arrays, Logic design, Pipelines, Proposals",

author = "O. Cadenas and G. Megson",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; Euromicro Symposium on Digital System Design, DSD 2002 ; Conference date: 04-09-2002 Through 06-09-2002",

year = "2002",

doi = "10.1109/DSD.2002.1115379",

language = "English",

series = "Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002",

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pages = "276--282",

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Cadenas, O & Megson, G 2002, Improving mW/MHz ratio in FPGAs pipelined designs. in M Edwards (ed.), Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002., 1115379, Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002, Institute of Electrical and Electronics Engineers Inc., pp. 276-282, Euromicro Symposium on Digital System Design, DSD 2002, Dortmund, Germany, 4/09/02. https://doi.org/10.1109/DSD.2002.1115379

Improving mW/MHz ratio in FPGAs pipelined designs. / Cadenas, O.; Megson, G.
Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002. ed. / Martyn Edwards. Institute of Electrical and Electronics Engineers Inc., 2002. p. 276-282 1115379 (Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.

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KW - Design engineering

KW - Energy consumption

KW - Field programmable gate arrays

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Cadenas O, Megson G. Improving mW/MHz ratio in FPGAs pipelined designs. In Edwards M, editor, Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 276-282. 1115379. (Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods and Tools, DSD 2002). doi: 10.1109/DSD.2002.1115379

Improving mW/MHz ratio in FPGAs pipelined designs

Abstract

Publication series

Conference

Bibliographical note

Keywords

UN SDGs

Access to Document

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Cite this