Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs

Oswaldo Cadenas; Mark Alexander Brandt; Graham Megson; Nomita Goswami

Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs

Oswaldo Cadenas, Mark Alexander Brandt, Graham Megson, Nomita Goswami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level.

Original language	English
Title of host publication	2004 IEEE International Symposium on Consumer Electronics - Proceedings
Pages	465-469
Number of pages	5
Publication status	Published - 2004
Externally published	Yes
Event	2004 IEEE International Symposium on Consumer Electronics - Proceedings - Reading, United Kingdom Duration: 1 Sept 2004 → 3 Sept 2004

Publication series

Name	2004 IEEE International Symposium on Consumer Electronics - Proceedings

Conference

Conference	2004 IEEE International Symposium on Consumer Electronics - Proceedings
Country/Territory	United Kingdom
City	Reading
Period	1/09/04 → 3/09/04

Keywords

FPGA
Inverse DCT
Low power
Pipelining

Cite this

@inproceedings{8df7164c290f4f9eb2bd02f6a29d822e,

title = "Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs",

abstract = "Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level.",

keywords = "FPGA, Inverse DCT, Low power, Pipelining",

author = "Oswaldo Cadenas and Brandt, {Mark Alexander} and Graham Megson and Nomita Goswami",

year = "2004",

language = "English",

isbn = "0780385276",

series = "2004 IEEE International Symposium on Consumer Electronics - Proceedings",

pages = "465--469",

booktitle = "2004 IEEE International Symposium on Consumer Electronics - Proceedings",

note = "2004 IEEE International Symposium on Consumer Electronics - Proceedings ; Conference date: 01-09-2004 Through 03-09-2004",

}

Cadenas, O, Brandt, MA, Megson, G & Goswami, N 2004, Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs. in 2004 IEEE International Symposium on Consumer Electronics - Proceedings. 2004 IEEE International Symposium on Consumer Electronics - Proceedings, pp. 465-469, 2004 IEEE International Symposium on Consumer Electronics - Proceedings, Reading, United Kingdom, 1/09/04.

Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs. / Cadenas, Oswaldo; Brandt, Mark Alexander; Megson, Graham et al.
2004 IEEE International Symposium on Consumer Electronics - Proceedings. 2004. p. 465-469 (2004 IEEE International Symposium on Consumer Electronics - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs

AU - Cadenas, Oswaldo

AU - Brandt, Mark Alexander

AU - Megson, Graham

AU - Goswami, Nomita

PY - 2004

Y1 - 2004

N2 - Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level.

AB - Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level.

KW - FPGA

KW - Inverse DCT

KW - Low power

KW - Pipelining

UR - http://www.scopus.com/inward/record.url?scp=10444252455&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:10444252455

SN - 0780385276

T3 - 2004 IEEE International Symposium on Consumer Electronics - Proceedings

SP - 465

EP - 469

BT - 2004 IEEE International Symposium on Consumer Electronics - Proceedings

T2 - 2004 IEEE International Symposium on Consumer Electronics - Proceedings

Y2 - 1 September 2004 through 3 September 2004

ER -

Investigation into low power of a 2D inverse discrete cosine transform (IDCT) in FPGAs

Abstract

Publication series

Conference

Keywords

Other files and links

Cite this