Median architecture by accumulative parallel counters

Oswaldo Cadenas

doi:10.1109/TCSII.2015.2415655

Median architecture by accumulative parallel counters

Oswaldo Cadenas

Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.

Original language	English
Pages (from-to)	661-665
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
DOIs	https://doi.org/10.1109/TCSII.2015.2415655
Publication status	Published - 23 Mar 2015

Keywords

0906 Electrical And Electronic Engineering
Electrical & Electronic Engineering
Pipelined architectures
Median

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10.1109/TCSII.2015.2415655Licence: CC BY 4.0

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title = "Median architecture by accumulative parallel counters",

abstract = "The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.",

keywords = "0906 Electrical And Electronic Engineering, Electrical & Electronic Engineering, Pipelined architectures, Median",

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AB - The time to process each of W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared to the literature. Parallelism uncovered in blocks containing B-bit slices are exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers for which a pipelined architecture is developed. An extra benefit of smaller area for the architecture is also reported.

KW - 0906 Electrical And Electronic Engineering

KW - Electrical & Electronic Engineering

KW - Pipelined architectures

KW - Median

U2 - 10.1109/TCSII.2015.2415655

DO - 10.1109/TCSII.2015.2415655

M3 - Article

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EP - 665

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

ER -

Median architecture by accumulative parallel counters

Abstract

Keywords

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