Median Filter Architecture by Accumulative Parallel Counters

Oswaldo Cadenas; Graham M. Megson; R. Simon Sherratt

doi:10.1109/TCSII.2015.2415655

Median Filter Architecture by Accumulative Parallel Counters

Oswaldo Cadenas, Graham M. Megson, R. Simon Sherratt

Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

The time to process each of the W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared with literature. The parallelism uncovered in blocks containing B-bit slices is exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers, for which a pipelined architecture is developed. An extra benefit of a smaller area for the architecture is also reported.

Original language	English
Article number	7065320
Pages (from-to)	661-665
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	62
Issue number	7
DOIs	https://doi.org/10.1109/TCSII.2015.2415655 https://doi.org/10.1109/TCSII.2015.2415655
Publication status	Published - 23 Mar 2015

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

0906 Electrical And Electronic Engineering
Electrical & Electronic Engineering
Pipelined architectures
Median

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abstract = "The time to process each of the W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared with literature. The parallelism uncovered in blocks containing B-bit slices is exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers, for which a pipelined architecture is developed. An extra benefit of a smaller area for the architecture is also reported.",

keywords = "0906 Electrical And Electronic Engineering, Electrical & Electronic Engineering, Pipelined architectures, Median",

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AB - The time to process each of the W/B processing blocks of a median calculation method on a set of N W-bit integers is improved here by a factor of three compared with literature. The parallelism uncovered in blocks containing B-bit slices is exploited by independent accumulative parallel counters so that the median is calculated faster than any known previous method for any N, W values. The improvements to the method are discussed in the context of calculating the median for a moving set of N integers, for which a pipelined architecture is developed. An extra benefit of a smaller area for the architecture is also reported.

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JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

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Median Filter Architecture by Accumulative Parallel Counters

Abstract

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Keywords

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