Pipelining considerations for an FPGA case

O. Cadenas; G. Megson

doi:10.1109/DSD.2001.952298

Pipelining considerations for an FPGA case

O. Cadenas, G. Megson

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Citations (Scopus)

Abstract

This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.

Original language	English
Title of host publication	Proceedings - Euromicro Symposium on Digital Systems Design
Subtitle of host publication	Architectures, Methods and Tools, DSD 2001
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	276-283
Number of pages	8
ISBN (Electronic)	0769512399, 9780769512396
DOIs	https://doi.org/10.1109/DSD.2001.952298
Publication status	Published - 2001
Externally published	Yes
Event	Euromicro Symposium on Digital Systems Design, DSD 2001 - Warsaw, Poland Duration: 4 Sept 2001 → 6 Sept 2001

Publication series

Name	Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001

Conference

Conference	Euromicro Symposium on Digital Systems Design, DSD 2001
Country/Territory	Poland
City	Warsaw
Period	4/09/01 → 6/09/01

Bibliographical note

Publisher Copyright:
© 2001 IEEE.

Access to Document

10.1109/DSD.2001.952298

Cite this

Cadenas, O., & Megson, G. (2001). Pipelining considerations for an FPGA case. In Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001 (pp. 276-283). Article 952298 (Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DSD.2001.952298

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title = "Pipelining considerations for an FPGA case",

abstract = "This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.",

author = "O. Cadenas and G. Megson",

note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; Euromicro Symposium on Digital Systems Design, DSD 2001 ; Conference date: 04-09-2001 Through 06-09-2001",

year = "2001",

doi = "10.1109/DSD.2001.952298",

language = "English",

series = "Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001",

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Cadenas, O & Megson, G 2001, Pipelining considerations for an FPGA case. in Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001., 952298, Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001, Institute of Electrical and Electronics Engineers Inc., pp. 276-283, Euromicro Symposium on Digital Systems Design, DSD 2001, Warsaw, Poland, 4/09/01. https://doi.org/10.1109/DSD.2001.952298

Pipelining considerations for an FPGA case. / Cadenas, O.; Megson, G.
Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 276-283 952298 (Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Megson, G.

PY - 2001

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N2 - This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.

AB - This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.

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U2 - 10.1109/DSD.2001.952298

DO - 10.1109/DSD.2001.952298

M3 - Conference contribution

AN - SCOPUS:84969557124

T3 - Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001

SP - 276

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BT - Proceedings - Euromicro Symposium on Digital Systems Design

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - Euromicro Symposium on Digital Systems Design, DSD 2001

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ER -

Cadenas O, Megson G. Pipelining considerations for an FPGA case. In Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 276-283. 952298. (Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001). doi: 10.1109/DSD.2001.952298

Pipelining considerations for an FPGA case

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