Power performance with gated clocks of a pipelined Cordic Core

Oswaldo Cadenas; Graham Megson

doi:10.1109/ICASIC.2003.1277435

Power performance with gated clocks of a pipelined Cordic Core

Oswaldo Cadenas, Graham Megson

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Citations (Scopus)

Abstract

This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Firtex-based FPGA de\'ices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops are used when synthesized with FPGA logic resources..

Original language	English
Title of host publication	ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings
Editors	Ting-Ao Tang, Wenhong Li, Huihua Yu
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1226-1230
Number of pages	5
ISBN (Electronic)	078037889X
DOIs	https://doi.org/10.1109/ICASIC.2003.1277435
Publication status	Published - 2003
Externally published	Yes
Event	5th International Conference on ASIC, ASICON 2003 - Beijing, China Duration: 21 Oct 2003 → 24 Oct 2003

Publication series

Name	IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings
Volume	2
ISSN (Print)	1523-553X

Conference

Conference	5th International Conference on ASIC, ASICON 2003
Country/Territory	China
City	Beijing
Period	21/10/03 → 24/10/03

Bibliographical note

Publisher Copyright:
© 2003 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

Access to Document

10.1109/ICASIC.2003.1277435

Cite this

Cadenas, O., & Megson, G. (2003). Power performance with gated clocks of a pipelined Cordic Core. In T.-A. Tang, W. Li, & H. Yu (Eds.), ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings (pp. 1226-1230). Article 5733623 (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICASIC.2003.1277435

Cadenas, Oswaldo ; Megson, Graham. / Power performance with gated clocks of a pipelined Cordic Core. ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings. editor / Ting-Ao Tang ; Wenhong Li ; Huihua Yu. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 1226-1230 (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings).

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title = "Power performance with gated clocks of a pipelined Cordic Core",

abstract = "This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Firtex-based FPGA de\'ices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops are used when synthesized with FPGA logic resources..",

author = "Oswaldo Cadenas and Graham Megson",

note = "Publisher Copyright: {\textcopyright} 2003 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.; 5th International Conference on ASIC, ASICON 2003 ; Conference date: 21-10-2003 Through 24-10-2003",

year = "2003",

doi = "10.1109/ICASIC.2003.1277435",

language = "English",

series = "IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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editor = "Ting-Ao Tang and Wenhong Li and Huihua Yu",

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Cadenas, O & Megson, G 2003, Power performance with gated clocks of a pipelined Cordic Core. in T-A Tang, W Li & H Yu (eds), ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings., 5733623, IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 1226-1230, 5th International Conference on ASIC, ASICON 2003, Beijing, China, 21/10/03. https://doi.org/10.1109/ICASIC.2003.1277435

Power performance with gated clocks of a pipelined Cordic Core. / Cadenas, Oswaldo; Megson, Graham.
ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings. ed. / Ting-Ao Tang; Wenhong Li; Huihua Yu. Institute of Electrical and Electronics Engineers Inc., 2003. p. 1226-1230 5733623 (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Firtex-based FPGA de\'ices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops are used when synthesized with FPGA logic resources..

AB - This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Firtex-based FPGA de\'ices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops are used when synthesized with FPGA logic resources..

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M3 - Conference contribution

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T3 - IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

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Cadenas O, Megson G. Power performance with gated clocks of a pipelined Cordic Core. In Tang TA, Li W, Yu H, editors, ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2003. p. 1226-1230. 5733623. (IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings). doi: 10.1109/ICASIC.2003.1277435

Power performance with gated clocks of a pipelined Cordic Core

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Bibliographical note

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