Pullpipelining: A technique for systolic pipelined circuits

O. Cadenas; G. Megson

doi:10.1109/IWSOC.2003.1213036

Pullpipelining: A technique for systolic pipelined circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed. Control circuits using a synchronous, a semisynchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.

Original language	English
Title of host publication	Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
Editors	Yehya Ismail, Wael Badawy
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	205-210
Number of pages	6
ISBN (Electronic)	076951944X, 9780769519449
DOIs	https://doi.org/10.1109/IWSOC.2003.1213036
Publication status	Published - 2003
Externally published	Yes
Event	3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 - Calgary, Canada Duration: 30 Jun 2003 → 2 Jul 2003

Publication series

Name	Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Conference

Conference	3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
Country/Territory	Canada
City	Calgary
Period	30/06/03 → 2/07/03

Bibliographical note

Publisher Copyright:
© 2003 IEEE.

Keywords

Circuit simulation
Computational modeling
Data engineering
Pipeline processing
Proposals
Reduced instruction set computing
Registers
Runtime
Systems engineering and theory
Systolic arrays

Access to Document

10.1109/IWSOC.2003.1213036

Cite this

Cadenas, O., & Megson, G. (2003). Pullpipelining: A technique for systolic pipelined circuits. In Y. Ismail, & W. Badawy (Eds.), Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 (pp. 205-210). Article 1213036 (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IWSOC.2003.1213036

Cadenas, O. ; Megson, G. / Pullpipelining : A technique for systolic pipelined circuits. Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003. editor / Yehya Ismail ; Wael Badawy. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 205-210 (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003).

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abstract = "Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed. Control circuits using a synchronous, a semisynchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.",

keywords = "Circuit simulation, Computational modeling, Data engineering, Pipeline processing, Proposals, Reduced instruction set computing, Registers, Runtime, Systems engineering and theory, Systolic arrays",

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note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 ; Conference date: 30-06-2003 Through 02-07-2003",

year = "2003",

doi = "10.1109/IWSOC.2003.1213036",

language = "English",

series = "Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Cadenas, O & Megson, G 2003, Pullpipelining: A technique for systolic pipelined circuits. in Y Ismail & W Badawy (eds), Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003., 1213036, Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 205-210, 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003, Calgary, Canada, 30/06/03. https://doi.org/10.1109/IWSOC.2003.1213036

Pullpipelining: A technique for systolic pipelined circuits. / Cadenas, O.; Megson, G.
Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003. ed. / Yehya Ismail; Wael Badawy. Institute of Electrical and Electronics Engineers Inc., 2003. p. 205-210 1213036 (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Cadenas O, Megson G. Pullpipelining: A technique for systolic pipelined circuits. In Ismail Y, Badawy W, editors, Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 205-210. 1213036. (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003). doi: 10.1109/IWSOC.2003.1213036

Pullpipelining: A technique for systolic pipelined circuits

Abstract

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Bibliographical note

Keywords

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