Abstract
‘Encrypted computing’ is an approach to preventing
insider attacks by the privileged operator against the unprivileged user on a computing system. It requires a processor that works natively on encrypted data in user mode, and the security barrier that protects the user is hardware-based encryption, not access. We report on progress and practical experience with our superscalar RISC class prototype
processor for encrypted computing and supporting software
infrastructure. This paper aims to alert the secure hardware
community that encrypted computing is possibly practical, as
well as theoretically plausible. It has been shown formally
impossible for operator mode to read (or write to order) the
plaintext form of data originating from or being operated on
in the user mode of this class of processor, given that the
encryption is independently secure. Now we report standard
Dhrystone benchmarks for the prototype, showing performance
with AES-128 like a 433 MHz classic Pentium (1 GHz
base clock), thousands of times faster than other approaches
Original language | English |
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DOIs | |
Publication status | Published - 23 Apr 2018 |
Externally published | Yes |
Event | 2018 IEEE European Symposium on Security and Privacy Workshops - Duration: 23 Apr 2018 → … |
Conference
Conference | 2018 IEEE European Symposium on Security and Privacy Workshops |
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Period | 23/04/18 → … |